Model { Name "Simulator_2" Version 7.4 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.988" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 Created "Fri Oct 02 16:36:41 2009" Creator "manip07" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "manip13" ModifiedDateFormat "%" LastModifiedDate "Fri Oct 25 13:27:44 2013" RTWModifiedTimeStamp 304608463 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks on SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.6.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.6.0" StartTime "0.0" StopTime "30" AbsTol "auto" FixedStep "0.00125" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.6.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.6.0" Array { Type "Cell" Dimension 4 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "NoFixptDivByZeroProtection" Cell "OptimizeModelRefInitCode" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off EnforceIntegerDowncast on ExpressionFolding on BooleansAsBitfields off EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off } Simulink.DebuggingCC { $ObjectID 5 Version "1.6.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" StrictBusMsg "Warning" LoggingUnavailableSignals "error" BlockIODiagnostic "none" } Simulink.HardwareCC { $ObjectID 6 Version "1.6.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.6.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.SFSimCC { $ObjectID 8 Version "1.6.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.6.0" Array { Type "Cell" Dimension 2 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.6.0" Array { Type "Cell" Dimension 16 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.6.0" Array { Type "Cell" Dimension 15 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" ExtraOptions "-aGenerateTraceInfo=0 " CurrentDlgPage "Hardware Implementation" ConfigPrmDlgPosition " [ 520, 225, 1400, 855 ] " } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Arial" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeMode "Inherit from 'Constant value'" OutDataType "fixdt(1,16,0)" ConRadixGroup "Use specified scaling" OutScaling "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" } Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType DiscreteFilter Numerator "[1]" Denominator "[1 0.5]" InitialStates "0" SampleTime "-1" a0EqualsOne off NumCoefMin "[]" NumCoefMax "[]" DenCoefMin "[]" DenCoefMax "[]" OutMin "[]" OutMax "[]" StateDataTypeStr "Inherit: Same as input" NumCoefDataTypeStr "Inherit: Inherit via internal rule" DenCoefDataTypeStr "Inherit: Inherit via internal rule" NumProductDataTypeStr "Inherit: Inherit via internal rule" DenProductDataTypeStr "Inherit: Inherit via internal rule" NumAccumDataTypeStr "Inherit: Inherit via internal rule" DenAccumDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow off StateMustResolveToSignalObject off RTWStateStorageClass "Auto" } Block { BlockType DiscreteIntegrator IntegratorMethod "Integration: Forward Euler" gainval "1.0" ExternalReset "none" InitialConditionSource "internal" InitialCondition "0" InitialConditionMode "State and output" SampleTime "1" OutMin "[]" OutMax "[]" OutDataTypeMode "Inherit via internal rule" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow off LimitOutput off UpperSaturationLimit "inf" LowerSaturationLimit "-inf" ShowSaturationPort off ShowStatePort off IgnoreLimit off StateMustResolveToSignalObject off RTWStateStorageClass "Auto" } Block { BlockType EnablePort StatesWhenEnabling "held" PropagateVarSize "Only when enabling" ShowOutputPort off ZeroCross on } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ParamMin "[]" ParamMax "[]" ParameterDataTypeMode "Same as input" ParameterDataType "fixdt(1,16,0)" ParameterScalingMode "Best Precision: Matrix-wise" ParameterScaling "[]" ParamDataTypeStr "Inherit: Same as input" OutMin "[]" OutMax "[]" OutDataTypeMode "Same as input" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType Inport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" OutMin "[]" OutMax "[]" DataType "auto" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: auto" LockScale off SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchByCopyingInsideSignal off Interpolate on } Block { BlockType MultiPortSwitch Inputs "3" zeroidx off InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeMode "Inherit via internal rule" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" AllowDiffInputSizes off } Block { BlockType Mux Inputs "4" DisplayOption "none" UseBusObject off BusObject "BusObject" NonVirtualBus off } Block { BlockType Outport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" OutMin "[]" OutMax "[]" DataType "auto" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: auto" LockScale off SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Product Inputs "2" Multiplication "Element-wise(.*)" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeMode "Same as first input" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" SFunctionDeploymentMode off } Block { BlockType Saturate UpperLimit "0.5" LowerLimit "-0.5" LinearizeAsGain on ZeroCross on SampleTime "-1" OutMin "[]" OutMax "[]" OutDataTypeMode "Same as input" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Sin SineType "Time based" TimeSource "Use simulation time" SampleTime "-1" VectorParams1D on } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeMode "Same as first input" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } } System { Name "Simulator_2" Location [753, 143, 1785, 860] Open on ModelBrowserVisibility on ModelBrowserWidth 212 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark 286 Block { BlockType Constant Name "0 : OL\n1 : CL" SID 1 Position [230, 155, 260, 185] BlockRotation 270 BlockMirror on BackgroundColor "green" NamePlacement "alternate" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "Controller" SID 2 Ports [1, 1, 1] Position [200, 219, 290, 281] BackgroundColor "red" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskDisplay "disp('Controller')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" Port { PortNumber 1 Name "u(t)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Controller" Location [358, 109, 1217, 654] Open off ModelBrowserVisibility on ModelBrowserWidth 212 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "y(t)" SID 3 Position [110, 68, 140, 82] BackgroundColor "cyan" IconDisplay "Port number" } Block { BlockType EnablePort Name "Enable" SID 4 Ports [] Position [30, 15, 50, 35] } Block { BlockType Outport Name "u(t)" SID 5 Position [470, 68, 500, 82] BackgroundColor "red" IconDisplay "Port number" } } } Block { BlockType SubSystem Name "Disturbances" SID 6 Ports [0, 1] Position [100, 87, 200, 133] BackgroundColor "orange" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Disturbance Generator" MaskDescription "This block is designed to introduce the disturbance to the Benchmark simu-\nlator, accord" "ing with the three protocols describen in the website:\nSimple Step Test, Step Frequency Changes Test and Chirp " "Test." MaskPromptString "Test (1: Simple Step, 2: Step Changes, 3: Chirp)|Level (number of sinusoids [1,2,3])|Amp" "litude of the disturbance|Disturbance time (sec)|Disturbance remotion (sec)|Disturbance Frequency (Hz) [f1,f2,f3" "]|Step duration (sec)|Last step duration (sec)|First disturbance frequency vector (Hz) [f1,f2,f3]|Second disturb" "ance frequency vector (Hz) [f1,f2,f3]|Third disturbance frequency vector (Hz) [f1,f2,f3]|Instant of the injectio" "n of the first sequence (sec)|1st application of the chirp (sec)|2nd application of the chirp (sec)|Chirp durati" "on (sec)|Initial frequency sequence (Hz) [f1,f2,f3] [Fbeg]|Final frequency sequence (Hz) [f1,f2,f3] [Ffin]" MaskStyleString "edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "off,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskCallbackString "||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskVariables "test=@1;level=@2;amp=@3;Td=@4;RD=@5;Freq=@6;DD=@7;TL=@8;Freq1=@9;Freq2=@10;Freq3=@11;T0=@12" ";T1=@13;T2=@14;Tb=@15;Fbeg=@16;Ffin=@17;" MaskInitialization "if test<=0, test=1; end\nif level<=0, level=1; end\nif amp<=0, amp=0.1; end\nif Td<=0, " "Td=5; end\nif RD<=0, RD=20; end\nif length(Freq)<3, Freq=[0,0,0]; end\nif DD<=0, DD=3; end\nif TL<=0, TL=3; end\n" "if length(Freq1)<2\n Freq1=[Freq1,0,0];\nelseif length(Freq1)<3\n Freq1=[Freq1,0];\nend\nif length(Freq2)<" "2\n Freq2=[Freq2,0,0];\nelseif length(Freq2)<3\n Freq2=[Freq2,0];\nend\nif length(Freq3)<2\n Freq3=[Fre" "q1,0,0];\nelseif length(Freq3)<3\n Freq3=[Freq3,0];\nend\nif T0<=0, T0=5; end\nif T1<=0, T1=10; end\nif T2<=0" ", T2=5; end\nif Tb<=0, Tb=5; end\nif length(Fbeg)<=2\n Fbeg=[Fbeg,0,0];\nelseif length(Fbeg)<3\n Fbeg=[Fbe" "g,0];\nend\nif length(Ffin)<=2\n Ffin=[Ffin,0,0];\nelseif length(Ffin)<3\n Ffin=[Ffin,0];\nend" MaskDisplay "disp('Disturbance')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "1|1|0.1|5|20|[50,0,0]|0|0|0|0|0|0|0|0|0|0|0" MaskTabNameString "Test,Test,Test,Simple Step,Simple Step,Simple Step,Step Changes,Step Changes,Step Chang" "es,Step Changes,Step Changes,Chirp,Chirp,Chirp,Chirp,Chirp,Chirp" System { Name "Disturbances" Location [753, 143, 1785, 860] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType SubSystem Name " perturbation sinusoidale4" SID 7 Ports [0, 1, 1] Position [295, 337, 455, 363] BackgroundColor "yellow" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "sinusoidal disturbances block" MaskHelp "With this simulink block, one can define his sinusoidal disturbances.\nEnter\nLevel allow us to define" " number of sinusoids to inject into process in the same time.\n\nVector containing frequencies: allow un to choose " "disturbances frequencies to be injected in the same time. \n\nExample: [80;100;120] to inject three sinusoids of 80" ", 100, and 120Hz as first disturbance.\n\nPS: for the first (second level) just the first (first and second) freque" "ncies are considered.\n\nThe experimental protocol is define as:\n\n[sequence1 sequence2 sequence1 sequence3 sequen" "ce1]\n\nt0: is the start time to inject disturbances.\n\nT: is the time delay between two sequences.\n\nAmp: is the" " amplitude of each sinusoid." MaskPromptString "Level (n for n sinusoids)|Vector containing first disturbance frequencies sequence [f1;f2;f3] (" "put 0 if not needed) (Hz)|Vector containing second disturbance frequencies sequence [f1;f2;f3] (put 0 if not needed" ") (Hz)|Vector containing third disturbance frequencies sequence [f1;f2;f3] (put 0 if not needed) (Hz)|Start disturb" "ances time (sec)|Time delay between two disturbances (sec)|Duration of the last disturbance|Amplitude|Sample time (" "put 0)" MaskStyleString "edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on,on,on,on,on" MaskCallbackString "||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on,on,on" MaskVariables "level=@1;freq1=@2;freq2=@3;freq3=@4;t0=@5;T=@6;TL=@7;Amp=@8;Te=@9;" MaskDisplay "disp('Multi-Sinusoïsdal Disturbances')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "level|Freq1|Freq2|Freq3|Td|DD|TL|amp|0" System { Name " perturbation sinusoidale4" Location [2, 78, 1261, 897] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType EnablePort Name "Enable" SID 8 Ports [] Position [65, 30, 85, 50] } Block { BlockType Constant Name "Constant" SID 9 Position [710, 940, 740, 970] Value "level" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType From Name "From" SID 10 Position [755, 971, 795, 999] CloseFcn "tagdialog Close" GotoTag "A" } Block { BlockType From Name "From1" SID 11 Position [805, 1001, 845, 1029] CloseFcn "tagdialog Close" GotoTag "B" } Block { BlockType From Name "From2" SID 12 Position [850, 1031, 890, 1059] CloseFcn "tagdialog Close" GotoTag "C" } Block { BlockType Goto Name "Goto" SID 13 Position [585, 460, 625, 490] GotoTag "B" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID 14 Position [1850, 580, 1890, 610] GotoTag "C" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID 15 Position [1205, 520, 1245, 550] GotoTag "A" TagVisibility "local" } Block { BlockType MultiPortSwitch Name "Multiport\nSwitch" SID 16 Ports [4, 1] Position [930, 942, 960, 1058] InputSameDT off OutDataType "sfix(16)" OutScaling "2^0" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product1" SID 17 Ports [3, 1] Position [335, 158, 365, 192] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product10" SID 18 Ports [3, 1] Position [860, 708, 890, 742] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID 19 Ports [3, 1] Position [1525, 108, 1555, 142] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID 20 Ports [3, 1] Position [1530, 258, 1560, 292] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID 21 Ports [3, 1] Position [1525, 498, 1555, 532] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID 22 Ports [3, 1] Position [1560, 648, 1590, 682] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID 23 Ports [3, 1] Position [1560, 853, 1590, 887] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product2" SID 24 Ports [3, 1] Position [335, 278, 365, 312] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product3" SID 25 Ports [3, 1] Position [335, 398, 365, 432] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product4" SID 26 Ports [3, 1] Position [335, 508, 365, 542] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product5" SID 27 Ports [3, 1] Position [340, 633, 370, 667] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product6" SID 28 Ports [3, 1] Position [870, 203, 900, 237] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product7" SID 29 Ports [3, 1] Position [870, 323, 900, 357] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID 30 Ports [3, 1] Position [870, 453, 900, 487] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID 31 Ports [3, 1] Position [865, 588, 895, 622] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sin Name "Sine Wave1" SID 32 Ports [0, 1] Position [165, 175, 195, 205] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave10" SID 33 Ports [0, 1] Position [740, 205, 770, 235] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave11" SID 34 Ports [0, 1] Position [160, 615, 190, 645] NamePlacement "alternate" Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave12" SID 35 Ports [0, 1] Position [740, 325, 770, 355] Amplitude "Amp" Bias "0" Frequency "freq2(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave13" SID 36 Ports [0, 1] Position [740, 455, 770, 485] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave14" SID 37 Ports [0, 1] Position [730, 590, 760, 620] Amplitude "Amp" Bias "0" Frequency "freq3(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave15" SID 38 Ports [0, 1] Position [730, 710, 760, 740] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave16" SID 39 Ports [0, 1] Position [1275, 110, 1305, 140] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave17" SID 40 Ports [0, 1] Position [1285, 810, 1315, 840] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave18" SID 41 Ports [0, 1] Position [1270, 260, 1300, 290] Amplitude "Amp" Bias "0" Frequency "freq2(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave19" SID 42 Ports [0, 1] Position [1275, 65, 1305, 95] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave2" SID 43 Ports [0, 1] Position [160, 295, 190, 325] Amplitude "Amp" Bias "0" Frequency "freq2(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave20" SID 44 Ports [0, 1] Position [1270, 215, 1300, 245] Amplitude "Amp" Bias "0" Frequency "freq2(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave21" SID 45 Ports [0, 1] Position [1300, 500, 1330, 530] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave22" SID 46 Ports [0, 1] Position [1300, 650, 1330, 680] Amplitude "Amp" Bias "0" Frequency "freq3(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave23" SID 47 Ports [0, 1] Position [1300, 455, 1330, 485] Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave24" SID 48 Ports [0, 1] Position [1300, 605, 1330, 635] Amplitude "Amp" Bias "0" Frequency "freq3(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave25" SID 49 Ports [0, 1] Position [1285, 855, 1315, 885] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave26" SID 50 Ports [0, 1] Position [1275, 155, 1305, 185] Amplitude "Amp" Bias "0" Frequency "freq1(3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave27" SID 51 Ports [0, 1] Position [1270, 305, 1300, 335] Amplitude "Amp" Bias "0" Frequency "freq2(3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave28" SID 52 Ports [0, 1] Position [1300, 545, 1330, 575] Amplitude "Amp" Bias "0" Frequency "freq1(3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave29" SID 53 Ports [0, 1] Position [1300, 695, 1330, 725] Amplitude "Amp" Bias "0" Frequency "freq3(3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave3" SID 54 Ports [0, 1] Position [165, 140, 195, 170] NamePlacement "alternate" Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave30" SID 55 Ports [0, 1] Position [1285, 900, 1315, 930] Amplitude "Amp" Bias "0" Frequency "freq1(3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave4" SID 56 Ports [0, 1] Position [160, 260, 190, 290] NamePlacement "alternate" Amplitude "Amp" Bias "0" Frequency "freq2(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave5" SID 57 Ports [0, 1] Position [165, 420, 195, 450] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave6" SID 58 Ports [0, 1] Position [160, 530, 190, 560] Amplitude "Amp" Bias "0" Frequency "freq3(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave7" SID 59 Ports [0, 1] Position [165, 380, 195, 410] NamePlacement "alternate" Amplitude "Amp" Bias "0" Frequency "freq1(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave8" SID 60 Ports [0, 1] Position [160, 490, 190, 520] NamePlacement "alternate" Amplitude "Amp" Bias "0" Frequency "freq3(1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Sine Wave9" SID 61 Ports [0, 1] Position [160, 655, 190, 685] Amplitude "Amp" Bias "0" Frequency "freq1(2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Step Name "Step1" SID 62 Position [275, 180, 305, 210] Time "t0+T" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step10" SID 63 Position [275, 610, 305, 640] NamePlacement "alternate" Time "t0+T*4" SampleTime "0" } Block { BlockType Step Name "Step11" SID 64 Position [790, 180, 820, 210] NamePlacement "alternate" Time "t0" SampleTime "0" } Block { BlockType Step Name "Step12" SID 65 Position [790, 230, 820, 260] Time "t0+T" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step13" SID 66 Position [790, 300, 820, 330] NamePlacement "alternate" Time "t0+T" SampleTime "0" } Block { BlockType Step Name "Step14" SID 67 Position [790, 350, 820, 380] Time "t0+T*2" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step15" SID 68 Position [790, 430, 820, 460] NamePlacement "alternate" Time "t0+T*2" SampleTime "0" } Block { BlockType Step Name "Step16" SID 69 Position [790, 480, 820, 510] Time "t0+T*3" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step17" SID 70 Position [785, 565, 815, 595] NamePlacement "alternate" Time "t0+T*3" SampleTime "0" } Block { BlockType Step Name "Step18" SID 71 Position [785, 615, 815, 645] Time "t0+T*4" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step19" SID 72 Position [780, 685, 810, 715] NamePlacement "alternate" Time "t0+T*4" SampleTime "0" } Block { BlockType Step Name "Step2" SID 73 Position [275, 140, 305, 170] NamePlacement "alternate" Time "t0" SampleTime "0" } Block { BlockType Step Name "Step20" SID 74 Position [780, 730, 810, 760] Time "t0+T*4+TL" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step21" SID 75 Position [1460, 130, 1490, 160] Time "t0+T" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step22" SID 76 Position [1485, 835, 1515, 865] NamePlacement "alternate" Time "t0+T*4" SampleTime "0" } Block { BlockType Step Name "Step23" SID 77 Position [1460, 90, 1490, 120] NamePlacement "alternate" Time "t0" SampleTime "0" } Block { BlockType Step Name "Step24" SID 78 Position [1460, 280, 1490, 310] Time "t0+T*2" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step25" SID 79 Position [1460, 240, 1490, 270] NamePlacement "alternate" Time "t0+T" SampleTime "0" } Block { BlockType Step Name "Step26" SID 80 Position [1455, 520, 1485, 550] Time "t0+T*3" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step27" SID 81 Position [1455, 480, 1485, 510] NamePlacement "alternate" Time "t0+T*2" SampleTime "0" } Block { BlockType Step Name "Step28" SID 82 Position [1485, 670, 1515, 700] Time "t0+T*4" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step29" SID 83 Position [1485, 630, 1515, 660] NamePlacement "alternate" Time "t0+T*3" SampleTime "0" } Block { BlockType Step Name "Step3" SID 84 Position [275, 300, 305, 330] Time "t0+T*2" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step30" SID 85 Position [1485, 875, 1515, 905] Time "t0+T*4+TL" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step4" SID 86 Position [275, 260, 305, 290] NamePlacement "alternate" Time "t0+T" SampleTime "0" } Block { BlockType Step Name "Step5" SID 87 Position [275, 420, 305, 450] Time "t0+T*3" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step6" SID 88 Position [275, 375, 305, 405] NamePlacement "alternate" Time "t0+T*2" SampleTime "0" } Block { BlockType Step Name "Step7" SID 89 Position [275, 530, 305, 560] Time "t0+T*4" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step8" SID 90 Position [275, 490, 305, 520] NamePlacement "alternate" Time "t0+T*3" SampleTime "0" } Block { BlockType Step Name "Step9" SID 91 Position [275, 660, 305, 690] Time "t0+T*4+TL" Before "1" After "0" SampleTime "0" } Block { BlockType Sum Name "Sum1" SID 92 Ports [2, 1] Position [225, 157, 260, 193] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum10" SID 93 Ports [2, 1] Position [1025, 517, 1060, 553] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum11" SID 94 Ports [3, 1] Position [1145, 517, 1180, 553] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum12" SID 95 Ports [3, 1] Position [1365, 88, 1385, 162] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum13" SID 96 Ports [3, 1] Position [1365, 240, 1385, 310] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum14" SID 97 Ports [2, 1] Position [1665, 187, 1700, 223] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum15" SID 98 Ports [3, 1] Position [1375, 478, 1400, 552] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum16" SID 99 Ports [3, 1] Position [1380, 630, 1410, 700] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum17" SID 100 Ports [2, 1] Position [1675, 577, 1710, 613] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum18" SID 101 Ports [3, 1] Position [1775, 577, 1810, 613] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum19" SID 102 Ports [3, 1] Position [1365, 834, 1390, 906] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum2" SID 103 Ports [2, 1] Position [220, 277, 255, 313] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum3" SID 104 Ports [2, 1] Position [420, 222, 455, 258] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum4" SID 105 Ports [2, 1] Position [225, 397, 260, 433] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum5" SID 106 Ports [2, 1] Position [220, 507, 255, 543] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum6" SID 107 Ports [2, 1] Position [465, 457, 500, 493] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum7" SID 108 Ports [3, 1] Position [535, 457, 570, 493] BackgroundColor "yellow" ShowName off Inputs "+|+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum8" SID 109 Ports [2, 1] Position [225, 632, 260, 668] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Sum Name "Sum9" SID 110 Ports [2, 1] Position [1040, 262, 1075, 298] BackgroundColor "yellow" ShowName off Inputs "+|+" OutDataType "sfix(16)" OutScaling "2^0" SampleTime "Te" } Block { BlockType Outport Name "Out1" SID 111 Position [1040, 993, 1070, 1007] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 3 } Line { SrcBlock "From" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 2 } Line { SrcBlock "Sum18" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Sine Wave30" SrcPort 1 Points [30, 0] DstBlock "Sum19" DstPort 3 } Line { SrcBlock "Sine Wave29" SrcPort 1 Points [30, 0] DstBlock "Sum16" DstPort 3 } Line { SrcBlock "Sine Wave28" SrcPort 1 Points [25, 0] DstBlock "Sum15" DstPort 3 } Line { SrcBlock "Sine Wave27" SrcPort 1 Points [45, 0] DstBlock "Sum13" DstPort 3 } Line { SrcBlock "Sine Wave26" SrcPort 1 Points [40, 0] DstBlock "Sum12" DstPort 3 } Line { SrcBlock "Sum11" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Product12" SrcPort 1 Points [85, 0] DstBlock "Sum14" DstPort 2 } Line { SrcBlock "Sum17" SrcPort 1 DstBlock "Sum18" DstPort 2 } Line { SrcBlock "Sine Wave25" SrcPort 1 DstBlock "Sum19" DstPort 2 } Line { SrcBlock "Sine Wave22" SrcPort 1 DstBlock "Sum16" DstPort 2 } Line { SrcBlock "Sine Wave21" SrcPort 1 DstBlock "Sum15" DstPort 2 } Line { SrcBlock "Sine Wave16" SrcPort 1 DstBlock "Sum12" DstPort 2 } Line { SrcBlock "Sine Wave18" SrcPort 1 DstBlock "Sum13" DstPort 2 } Line { SrcBlock "Product14" SrcPort 1 Points [65, 0] DstBlock "Sum17" DstPort 2 } Line { SrcBlock "Step30" SrcPort 1 Points [25, 0] DstBlock "Product15" DstPort 3 } Line { SrcBlock "Product15" SrcPort 1 Points [165, 0] DstBlock "Sum18" DstPort 3 } Line { SrcBlock "Sine Wave17" SrcPort 1 Points [30, 0] DstBlock "Sum19" DstPort 1 } Line { SrcBlock "Sum19" SrcPort 1 DstBlock "Product15" DstPort 2 } Line { SrcBlock "Step22" SrcPort 1 Points [25, 0] DstBlock "Product15" DstPort 1 } Line { SrcBlock "Product13" SrcPort 1 Points [100, 0] DstBlock "Sum17" DstPort 1 } Line { SrcBlock "Step24" SrcPort 1 Points [0, -10] DstBlock "Product12" DstPort 3 } Line { SrcBlock "Step21" SrcPort 1 Points [0, -10] DstBlock "Product11" DstPort 3 } Line { SrcBlock "Step28" SrcPort 1 Points [25, 0] DstBlock "Product14" DstPort 3 } Line { SrcBlock "Sine Wave24" SrcPort 1 Points [30, 0] DstBlock "Sum16" DstPort 1 } Line { SrcBlock "Sum16" SrcPort 1 DstBlock "Product14" DstPort 2 } Line { SrcBlock "Step29" SrcPort 1 Points [25, 0] DstBlock "Product14" DstPort 1 } Line { SrcBlock "Step26" SrcPort 1 Points [0, -10] DstBlock "Product13" DstPort 3 } Line { SrcBlock "Sine Wave23" SrcPort 1 Points [25, 0] DstBlock "Sum15" DstPort 1 } Line { SrcBlock "Sum15" SrcPort 1 DstBlock "Product13" DstPort 2 } Line { SrcBlock "Step27" SrcPort 1 Points [0, 10] DstBlock "Product13" DstPort 1 } Line { SrcBlock "Sum14" SrcPort 1 Points [55, 0] DstBlock "Sum18" DstPort 1 } Line { SrcBlock "Product11" SrcPort 1 Points [90, 0] DstBlock "Sum14" DstPort 1 } Line { SrcBlock "Sine Wave20" SrcPort 1 Points [45, 0] DstBlock "Sum13" DstPort 1 } Line { SrcBlock "Sum13" SrcPort 1 DstBlock "Product12" DstPort 2 } Line { SrcBlock "Step25" SrcPort 1 Points [0, 10] DstBlock "Product12" DstPort 1 } Line { SrcBlock "Sine Wave19" SrcPort 1 Points [40, 0] DstBlock "Sum12" DstPort 1 } Line { SrcBlock "Sum12" SrcPort 1 DstBlock "Product11" DstPort 2 } Line { SrcBlock "Step23" SrcPort 1 Points [0, 10] DstBlock "Product11" DstPort 1 } Line { SrcBlock "Sum10" SrcPort 1 DstBlock "Sum11" DstPort 2 } Line { SrcBlock "Sum9" SrcPort 1 Points [35, 0; 0, 245] DstBlock "Sum11" DstPort 1 } Line { SrcBlock "Product10" SrcPort 1 Points [220, 0; 0, -180] DstBlock "Sum11" DstPort 3 } Line { SrcBlock "Step20" SrcPort 1 Points [10, 0; 0, -10] DstBlock "Product10" DstPort 3 } Line { SrcBlock "Sine Wave15" SrcPort 1 DstBlock "Product10" DstPort 2 } Line { SrcBlock "Step19" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Product10" DstPort 1 } Line { SrcBlock "Product9" SrcPort 1 Points [60, 0; 0, -60] DstBlock "Sum10" DstPort 2 } Line { SrcBlock "Step18" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Product9" DstPort 3 } Line { SrcBlock "Sine Wave14" SrcPort 1 DstBlock "Product9" DstPort 2 } Line { SrcBlock "Step17" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Product9" DstPort 1 } Line { SrcBlock "Product8" SrcPort 1 Points [55, 0; 0, 55] DstBlock "Sum10" DstPort 1 } Line { SrcBlock "Step16" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Product8" DstPort 3 } Line { SrcBlock "Sine Wave13" SrcPort 1 DstBlock "Product8" DstPort 2 } Line { SrcBlock "Step15" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Product8" DstPort 1 } Line { SrcBlock "Sum7" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Product7" SrcPort 1 Points [60, 0; 0, -50] DstBlock "Sum9" DstPort 2 } Line { SrcBlock "Step14" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Product7" DstPort 3 } Line { SrcBlock "Sine Wave12" SrcPort 1 DstBlock "Product7" DstPort 2 } Line { SrcBlock "Step13" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Product7" DstPort 1 } Line { SrcBlock "Product6" SrcPort 1 Points [60, 0; 0, 50] DstBlock "Sum9" DstPort 1 } Line { SrcBlock "Step12" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Product6" DstPort 3 } Line { SrcBlock "Sine Wave10" SrcPort 1 DstBlock "Product6" DstPort 2 } Line { SrcBlock "Step11" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Product6" DstPort 1 } Line { SrcBlock "Multiport\nSwitch" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Product2" SrcPort 1 Points [35, 0] DstBlock "Sum3" DstPort 2 } Line { SrcBlock "Sum6" SrcPort 1 DstBlock "Sum7" DstPort 2 } Line { SrcBlock "Sine Wave9" SrcPort 1 Points [0, -10] DstBlock "Sum8" DstPort 2 } Line { SrcBlock "Sine Wave6" SrcPort 1 Points [0, -10] DstBlock "Sum5" DstPort 2 } Line { SrcBlock "Sine Wave5" SrcPort 1 Points [0, -10] DstBlock "Sum4" DstPort 2 } Line { SrcBlock "Sine Wave1" SrcPort 1 Points [10, 0] DstBlock "Sum1" DstPort 2 } Line { SrcBlock "Sine Wave2" SrcPort 1 Points [0, -5] DstBlock "Sum2" DstPort 2 } Line { SrcBlock "Product4" SrcPort 1 Points [35, 0; 0, -40] DstBlock "Sum6" DstPort 2 } Line { SrcBlock "Step9" SrcPort 1 Points [0, -15] DstBlock "Product5" DstPort 3 } Line { SrcBlock "Product5" SrcPort 1 Points [145, 0] DstBlock "Sum7" DstPort 3 } Line { SrcBlock "Sine Wave11" SrcPort 1 Points [0, 10] DstBlock "Sum8" DstPort 1 } Line { SrcBlock "Sum8" SrcPort 1 DstBlock "Product5" DstPort 2 } Line { SrcBlock "Step10" SrcPort 1 Points [0, 15] DstBlock "Product5" DstPort 1 } Line { SrcBlock "Product3" SrcPort 1 Points [35, 0; 0, 50] DstBlock "Sum6" DstPort 1 } Line { SrcBlock "Step3" SrcPort 1 Points [0, -10] DstBlock "Product2" DstPort 3 } Line { SrcBlock "Step1" SrcPort 1 Points [0, -10] DstBlock "Product1" DstPort 3 } Line { SrcBlock "Step7" SrcPort 1 Points [10, 0] DstBlock "Product4" DstPort 3 } Line { SrcBlock "Sine Wave8" SrcPort 1 Points [0, 10] DstBlock "Sum5" DstPort 1 } Line { SrcBlock "Sum5" SrcPort 1 DstBlock "Product4" DstPort 2 } Line { SrcBlock "Step8" SrcPort 1 Points [10, 0] DstBlock "Product4" DstPort 1 } Line { SrcBlock "Step5" SrcPort 1 Points [0, -10] DstBlock "Product3" DstPort 3 } Line { SrcBlock "Sine Wave7" SrcPort 1 Points [0, 10] DstBlock "Sum4" DstPort 1 } Line { SrcBlock "Sum4" SrcPort 1 DstBlock "Product3" DstPort 2 } Line { SrcBlock "Step6" SrcPort 1 Points [0, 15] DstBlock "Product3" DstPort 1 } Line { SrcBlock "Sum3" SrcPort 1 Points [60, 0] DstBlock "Sum7" DstPort 1 } Line { SrcBlock "Product1" SrcPort 1 Points [35, 0] DstBlock "Sum3" DstPort 1 } Line { SrcBlock "Sine Wave4" SrcPort 1 Points [0, 10] DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Sum2" SrcPort 1 DstBlock "Product2" DstPort 2 } Line { SrcBlock "Step4" SrcPort 1 Points [0, 10] DstBlock "Product2" DstPort 1 } Line { SrcBlock "Sine Wave3" SrcPort 1 Points [10, 0] DstBlock "Sum1" DstPort 1 } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Product1" DstPort 2 } Line { SrcBlock "Step2" SrcPort 1 Points [0, 10] DstBlock "Product1" DstPort 1 } } } Block { BlockType SubSystem Name "Disturbance" SID 112 Ports [0, 1, 1] Position [325, 270, 455, 300] BackgroundColor "yellow" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Amplitud|Frequency (Hz)|Apply disturbance (sec)|Remove disturbance (sec)" MaskStyleString "edit,edit,edit,edit" MaskTunableValueString "on,on,on,on" MaskCallbackString "|||" MaskEnableString "on,on,on,on" MaskVisibilityString "on,on,on,on" MaskToolTipString "on,on,on,on" MaskVariables "Amp=@1;Freq=@2;Tini=@3;Tfin=@4;" MaskDisplay "disp('Sinusoidal Disturbance')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "amp|Freq|Td|RD" System { Name "Disturbance" Location [746, 82, 1605, 627] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType EnablePort Name "Enable" SID 113 Ports [] Position [70, 25, 90, 45] } Block { BlockType Constant Name "Constant" SID 114 Position [180, 50, 210, 80] Value "level" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Sin Name "Disturbance" SID 115 Ports [0, 1] Position [60, 120, 90, 150] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Disturbance1" SID 116 Ports [0, 1] Position [60, 175, 90, 205] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Disturbance2" SID 117 Ports [0, 1] Position [60, 230, 90, 260] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Disturbance3" SID 118 Ports [0, 1] Position [60, 295, 90, 325] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,1)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Disturbance4" SID 119 Ports [0, 1] Position [60, 360, 90, 390] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,2)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType Sin Name "Disturbance5" SID 120 Ports [0, 1] Position [60, 425, 90, 455] BackgroundColor "green" Amplitude "Amp" Bias "0" Frequency "Freq(1,3)*2*pi" Phase "0" Samples "10" Offset "0" SampleTime "0" } Block { BlockType MultiPortSwitch Name "Multiport\nSwitch" SID 121 Ports [4, 1] Position [440, 117, 470, 163] InputSameDT off OutDataType "sfix(16)" OutScaling "2^0" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product" SID 122 Ports [3, 1] Position [655, 124, 685, 156] ShowName off Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Step Name "Step" SID 123 Position [540, 89, 570, 111] BackgroundColor "green" ShowName off Time "Tfin" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Step1" SID 124 Position [540, 169, 570, 191] BackgroundColor "green" ShowName off Time "Tini" SampleTime "0" } Block { BlockType Sum Name "Sum" SID 125 Ports [2, 1] Position [150, 205, 170, 225] ShowName off IconShape "round" Inputs "+|+" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum1" SID 126 Ports [3, 1] Position [175, 360, 205, 390] ShowName off IconShape "round" Inputs "+|+|+" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "Out1" SID 127 Position [720, 133, 750, 147] IconDisplay "Port number" } Line { SrcBlock "Step" SrcPort 1 Points [50, 0; 0, 30] DstBlock "Product" DstPort 1 } Line { SrcBlock "Step1" SrcPort 1 Points [50, 0; 0, -30] DstBlock "Product" DstPort 3 } Line { SrcBlock "Product" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Multiport\nSwitch" SrcPort 1 DstBlock "Product" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 Points [105, 0; 0, 60] DstBlock "Multiport\nSwitch" DstPort 1 } Line { SrcBlock "Disturbance" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 2 } Line { SrcBlock "Disturbance1" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Disturbance2" SrcPort 1 Points [65, 0] DstBlock "Sum" DstPort 2 } Line { SrcBlock "Sum" SrcPort 1 Points [125, 0; 0, -70] DstBlock "Multiport\nSwitch" DstPort 3 } Line { SrcBlock "Disturbance3" SrcPort 1 Points [95, 0] DstBlock "Sum1" DstPort 1 } Line { SrcBlock "Disturbance4" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "Disturbance5" SrcPort 1 Points [95, 0] DstBlock "Sum1" DstPort 3 } Line { SrcBlock "Sum1" SrcPort 1 Points [110, 0; 0, -220] DstBlock "Multiport\nSwitch" DstPort 4 } } } Block { BlockType MultiPortSwitch Name "Disturbance Selector" SID 128 Ports [4, 1] Position [600, 187, 630, 448] InputSameDT off OutDataType "sfix(16)" OutScaling "2^0" SaturateOnIntegerOverflow off } Block { BlockType Constant Name "F Chirp" SID 276 Position [55, 565, 85, 595] Value "Fbeg" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "F Simple" SID 274 Position [55, 450, 85, 480] Value "Freq" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "F Step" SID 275 Position [55, 510, 85, 540] Value "Freq1" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Goto Name "Goto" SID 271 Position [235, 130, 275, 160] GotoTag "Test" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID 277 Position [130, 450, 170, 480] GotoTag "Freq" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID 278 Position [130, 510, 170, 540] GotoTag "Freq1" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID 279 Position [130, 565, 170, 595] GotoTag "Fbeg" TagVisibility "global" } Block { BlockType Reference Name "Siimple Step" SID 129 Ports [1, 1] Position [185, 240, 215, 270] LibraryVersion "1.762" SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Constant" SourceType "Compare To Constant" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" relop "==" const "1" LogicOutDataTypeMode "uint8" ZeroCross off } Block { BlockType SubSystem Name "Stanislav" SID 130 Ports [0, 1, 1] Position [355, 403, 455, 427] BackgroundColor "orange" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "level|Initial frequency sequence (vector Fbeg) [Hz]|Final frequency sequence (vector Ffin) [Hz]" "|Amplitude (Amp)|Instant of the initial frequency sequence injection 'T0'|instant to run a chirp 'T1'|Transition ti" "me between Fbeg and Ffin ('Tb') \"slope=(Ffin-Fbeg)/Tb\"|Time duration of the final frequency sequence Ffin 'T2'|S" "ample time" MaskStyleString "edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on,on,on,on,on" MaskCallbackString "||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on,on,on" MaskVariables "n=@1;Fbeg=@2;Ffin=@3;amp=@4;T0=@5;T1=@6;Tb=@7;T2=@8;Te=@9;" MaskDisplay "disp ('Chirp Generator')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "level|Fbeg|Ffin|amp|T0|T1|Tb|T2|1/800" System { Name "Stanislav" Location [204, 155, 948, 453] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType EnablePort Name "Enable" SID 131 Ports [] Position [50, 40, 70, 60] } Block { BlockType Sum Name "Add" SID 132 Ports [4, 1] Position [110, 229, 145, 286] Inputs "++++" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add1" SID 133 Ports [3, 1] Position [880, 281, 915, 339] Inputs "+++" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType DiscreteIntegrator Name "Freq" SID 134 Ports [1, 1] Position [255, 129, 290, 161] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" InitialCondition "Fbeg(1)" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType DiscreteIntegrator Name "Freq*t" SID 135 Ports [1, 1] Position [330, 129, 365, 161] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType DiscreteIntegrator Name "Freq*t1" SID 136 Ports [1, 1] Position [335, 244, 370, 276] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType DiscreteIntegrator Name "Freq*t2" SID 137 Ports [1, 1] Position [335, 349, 370, 381] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType DiscreteIntegrator Name "Freq1" SID 138 Ports [1, 1] Position [260, 244, 295, 276] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" InitialCondition "Fbeg(2)" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType DiscreteIntegrator Name "Freq2" SID 139 Ports [1, 1] Position [260, 349, 295, 381] IntegratorMethod "Integration: Forward Euler" ExternalReset "none" InitialConditionSource "internal" InitialCondition "Fbeg(3)" SampleTime "Te" ICPrevOutput "DiscIntNeverNeededParam" ICPrevScaledInput "DiscIntNeverNeededParam" } Block { BlockType Gain Name "Fslope" SID 140 Position [200, 130, 230, 160] Gain "(Ffin(1)-Fbeg(1))/Tb" ParameterDataTypeMode "Inherit via internal rule" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Fslope1" SID 141 Position [205, 245, 235, 275] Gain "(Ffin(2)-Fbeg(2))/Tb" ParameterDataTypeMode "Inherit via internal rule" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Fslope2" SID 142 Position [205, 350, 235, 380] Gain "(Ffin(3)-Fbeg(3))/Tb" ParameterDataTypeMode "Inherit via internal rule" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "L2 or L3" SID 143 Ports [1, 1] Position [600, 300, 630, 330] LibraryVersion "1.762" SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Constant" SourceType "Compare To Constant" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" relop ">" const "1" LogicOutDataTypeMode "uint8" ZeroCross "on" } Block { BlockType Reference Name "L3" SID 144 Ports [1, 1] Position [510, 415, 540, 445] LibraryVersion "1.762" SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Constant" SourceType "Compare To Constant" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" relop ">" const "2" LogicOutDataTypeMode "uint8" ZeroCross "on" } Block { BlockType Product Name "Product" SID 145 Ports [3, 1] Position [995, 294, 1025, 326] Inputs "3" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product1" SID 146 Ports [2, 1] Position [595, 406, 625, 439] InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product2" SID 147 Ports [2, 1] Position [680, 291, 710, 324] InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Step Name "T0" SID 148 Position [935, 240, 965, 270] Time "T0" SampleTime "0" } Block { BlockType Step Name "T1" SID 149 Position [35, 130, 65, 160] Time "T1" SampleTime "0" } Block { BlockType Step Name "T1+2Tb+2T2" SID 150 Position [925, 360, 955, 390] Time "T1+2*Tb+2*T2" Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "T1+Tb" SID 151 Position [35, 200, 65, 230] Time "T1+Tb" After "-1" SampleTime "0" } Block { BlockType Step Name "T1+Tb+T2" SID 152 Position [35, 270, 65, 300] Time "T1+Tb+T2" After "-1" SampleTime "0" } Block { BlockType Step Name "T1+Tb+T2+Tb" SID 153 Position [35, 340, 65, 370] Time "T1+Tb+T2+Tb" SampleTime "0" } Block { BlockType Gain Name "amp" SID 154 Position [935, 295, 965, 325] Gain "amp" ParameterDataTypeMode "Inherit via internal rule" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeMode "Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Constant Name "n" SID 155 Position [435, 415, 465, 445] Value "n" } Block { BlockType Constant Name "n1" SID 156 Position [525, 300, 555, 330] Value "n" } Block { BlockType Fcn Name "sin(2*pi*Freq*t)" SID 157 Position [400, 130, 460, 160] Expr "sin(2*pi*u)" } Block { BlockType Fcn Name "sin(2*pi*Freq*t)1" SID 158 Position [405, 245, 465, 275] Expr "sin(2*pi*u)" } Block { BlockType Fcn Name "sin(2*pi*Freq*t)2" SID 159 Position [405, 350, 465, 380] Expr "sin(2*pi*u)" } Block { BlockType Outport Name "Out1" SID 160 Position [1060, 308, 1090, 322] IconDisplay "Port number" } Line { SrcBlock "Freq*t" SrcPort 1 DstBlock "sin(2*pi*Freq*t)" DstPort 1 } Line { SrcBlock "Freq" SrcPort 1 DstBlock "Freq*t" DstPort 1 } Line { SrcBlock "sin(2*pi*Freq*t)" SrcPort 1 Points [240, 0; 0, 120; 160, 0] DstBlock "Add1" DstPort 1 } Line { SrcBlock "Product" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "T0" SrcPort 1 Points [10, 0] DstBlock "Product" DstPort 1 } Line { SrcBlock "T1+2Tb+2T2" SrcPort 1 Points [10, 0; 0, -55] DstBlock "Product" DstPort 3 } Line { SrcBlock "T1" SrcPort 1 Points [20, 0; 0, 90] DstBlock "Add" DstPort 1 } Line { SrcBlock "T1+Tb" SrcPort 1 Points [10, 0; 0, 35] DstBlock "Add" DstPort 2 } Line { SrcBlock "T1+Tb+T2" SrcPort 1 Points [10, 0; 0, -20] DstBlock "Add" DstPort 3 } Line { SrcBlock "T1+Tb+T2+Tb" SrcPort 1 Points [20, 0; 0, -75] DstBlock "Add" DstPort 4 } Line { SrcBlock "Fslope" SrcPort 1 DstBlock "Freq" DstPort 1 } Line { SrcBlock "Freq*t1" SrcPort 1 DstBlock "sin(2*pi*Freq*t)1" DstPort 1 } Line { SrcBlock "Freq1" SrcPort 1 DstBlock "Freq*t1" DstPort 1 } Line { SrcBlock "sin(2*pi*Freq*t)1" SrcPort 1 Points [195, 0] DstBlock "Product2" DstPort 1 } Line { SrcBlock "Fslope1" SrcPort 1 DstBlock "Freq1" DstPort 1 } Line { SrcBlock "Fslope2" SrcPort 1 DstBlock "Freq2" DstPort 1 } Line { SrcBlock "sin(2*pi*Freq*t)2" SrcPort 1 Points [85, 0; 0, 50] DstBlock "Product1" DstPort 1 } Line { SrcBlock "Freq2" SrcPort 1 DstBlock "Freq*t2" DstPort 1 } Line { SrcBlock "Freq*t2" SrcPort 1 DstBlock "sin(2*pi*Freq*t)2" DstPort 1 } Line { SrcBlock "Add" SrcPort 1 Points [20, 0] Branch { DstBlock "Fslope1" DstPort 1 } Branch { Points [0, -115] DstBlock "Fslope" DstPort 1 } Branch { Points [0, 105] DstBlock "Fslope2" DstPort 1 } } Line { SrcBlock "Add1" SrcPort 1 DstBlock "amp" DstPort 1 } Line { SrcBlock "n" SrcPort 1 DstBlock "L3" DstPort 1 } Line { SrcBlock "L3" SrcPort 1 DstBlock "Product1" DstPort 2 } Line { SrcBlock "n1" SrcPort 1 DstBlock "L2 or L3" DstPort 1 } Line { SrcBlock "L2 or L3" SrcPort 1 DstBlock "Product2" DstPort 2 } Line { SrcBlock "Product2" SrcPort 1 DstBlock "Add1" DstPort 2 } Line { SrcBlock "Product1" SrcPort 1 Points [105, 0; 0, -75; 130, 0] DstBlock "Add1" DstPort 3 } Line { SrcBlock "amp" SrcPort 1 DstBlock "Product" DstPort 2 } } } Block { BlockType Reference Name "Step Changes" SID 161 Ports [1, 1] Position [185, 300, 215, 330] LibraryVersion "1.762" SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Constant" SourceType "Compare To Constant" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" relop "==" const "2" LogicOutDataTypeMode "uint8" ZeroCross off } Block { BlockType Reference Name "Step Changes1" SID 162 Ports [1, 1] Position [185, 365, 215, 395] LibraryVersion "1.762" SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Constant" SourceType "Compare To Constant" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" relop "==" const "3" LogicOutDataTypeMode "uint8" ZeroCross off } Block { BlockType Constant Name "Test Protocol" SID 163 Position [55, 205, 85, 235] Value "test" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "d(t)" SID 164 Position [670, 313, 700, 327] IconDisplay "Port number" } Line { SrcBlock "Test Protocol" SrcPort 1 Points [50, 0] Branch { DstBlock "Disturbance Selector" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "Siimple Step" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "Step Changes" DstPort 1 } Branch { Points [0, 65] DstBlock "Step Changes1" DstPort 1 } } } Branch { Points [0, -75] DstBlock "Goto" DstPort 1 } } Line { SrcBlock "Disturbance Selector" SrcPort 1 DstBlock "d(t)" DstPort 1 } Line { SrcBlock "Disturbance" SrcPort 1 DstBlock "Disturbance Selector" DstPort 2 } Line { SrcBlock " perturbation sinusoidale4" SrcPort 1 DstBlock "Disturbance Selector" DstPort 3 } Line { SrcBlock "Stanislav" SrcPort 1 DstBlock "Disturbance Selector" DstPort 4 } Line { SrcBlock "Siimple Step" SrcPort 1 DstBlock "Disturbance" DstPort enable } Line { SrcBlock "Step Changes" SrcPort 1 Points [155, 0] DstBlock " perturbation sinusoidale4" DstPort enable } Line { SrcBlock "Step Changes1" SrcPort 1 Points [185, 0] DstBlock "Stanislav" DstPort enable } Line { SrcBlock "F Simple" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "F Step" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "F Chirp" SrcPort 1 DstBlock "Goto3" DstPort 1 } } } Block { BlockType Goto Name "Goto" SID 239 Position [290, 187, 330, 203] BackgroundColor "green" ShowName off GotoTag "L" TagVisibility "global" } Block { BlockType Mux Name "Mux1" SID 165 Ports [3, 1] Position [620, 166, 625, 234] ShowName off Inputs "3" DisplayOption "bar" } Block { BlockType SubSystem Name "Plant" SID 166 Ports [2, 1] Position [440, 205, 555, 265] BackgroundColor "yellow" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskDescription "before running simulator, don't forget to load noise mat file." MaskInitialization "load model_sec2.mat\nload model_prim2.mat" MaskDisplay "disp('Process')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" Port { PortNumber 1 Name "y(t)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Plant" Location [358, 109, 1217, 654] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "U" SID 167 Position [55, 78, 85, 92] BackgroundColor "green" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "U1" SID 168 Position [55, 163, 85, 177] BackgroundColor "green" Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "CLnoise" SID 169 Ports [0, 1] Position [475, 225, 570, 255] BackgroundColor "green" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskInitialization "load noise.mat " MaskDisplay "disp('Closed loop noise')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "CLnoise" Location [753, 143, 1785, 860] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Constant Name "C5" SID 248 Position [385, 615, 415, 645] Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "Embedded\nMATLAB Function1" SID 246 Ports [5, 1] Position [145, 87, 280, 313] PermitHierarchicalResolution "ExplicitOnly" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskDisplay "disp('noise_selection');" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Embedded\nMATLAB Function1" Location [257, 457, 812, 717] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark 13 SIDPrevWatermark 13 Block { BlockType Inport Name "u" SID 1 Position [20, 101, 40, 119] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Freq" SID 10 Position [20, 136, 40, 154] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Freq1" SID 11 Position [20, 171, 40, 189] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Fbeg" SID 12 Position [20, 206, 40, 224] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "L" SID 13 Position [20, 246, 40, 264] Port "5" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID 7 Ports [1, 1] Position [270, 220, 320, 260] Outputs "1" } Block { BlockType "S-Function" Name " SFunction " SID 6 Tag "Stateflow S-Function Simulator_2 1" Ports [5, 2] Position [180, 100, 230, 220] FunctionName "sf_sfun" PortCounts "[5 2]" EnableBusSupport on Port { PortNumber 2 Name "y" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID 9 Position [460, 231, 480, 249] } Block { BlockType Outport Name "y" SID 5 Position [460, 101, 480, 119] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock "u" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "Freq" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "Freq1" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "Fbeg" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { SrcBlock "L" SrcPort 1 DstBlock " SFunction " DstPort 5 } Line { Name "y" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "y" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } } } Block { BlockType From Name "From" SID 247 Position [85, 276, 125, 304] ShowName off GotoTag "L" TagVisibility "global" } Block { BlockType From Name "From1" SID 273 Position [85, 96, 125, 124] GotoTag "Test" TagVisibility "global" } Block { BlockType From Name "From2" SID 280 Position [85, 141, 125, 169] GotoTag "Freq" TagVisibility "global" } Block { BlockType From Name "From3" SID 281 Position [85, 186, 125, 214] GotoTag "Freq1" TagVisibility "global" } Block { BlockType From Name "From4" SID 282 Position [85, 231, 125, 259] GotoTag "Fbeg" TagVisibility "global" } Block { BlockType MultiPortSwitch Name "Multiport\nSwitch" SID 241 Ports [12, 1] Position [455, 50, 495, 660] Inputs "11" InputSameDT off OutDataType "fixdt(1, 16)" OutScaling "2^0" SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "Subsystem" SID 260 Ports [0, 10] Position [340, 109, 385, 601] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [719, 228, 854, 760] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Noise 50" SID 173 Ports [0, 1] Position [25, 25, 55, 55] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise50" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 55" SID 174 Ports [0, 1] Position [25, 75, 55, 105] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise55" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 60" SID 175 Ports [0, 1] Position [25, 125, 55, 155] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise60" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 65" SID 176 Ports [0, 1] Position [25, 175, 55, 205] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise65" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 70" SID 177 Ports [0, 1] Position [25, 225, 55, 255] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise70" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 75" SID 178 Ports [0, 1] Position [25, 275, 55, 305] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise75" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 80" SID 179 Ports [0, 1] Position [25, 325, 55, 355] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise80" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 85" SID 180 Ports [0, 1] Position [25, 375, 55, 405] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise85" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 90" SID 181 Ports [0, 1] Position [25, 425, 55, 455] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise90" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 95" SID 182 Ports [0, 1] Position [25, 475, 55, 505] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise95" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Outport Name "Out1" SID 261 Position [80, 33, 110, 47] IconDisplay "Port number" } Block { BlockType Outport Name "Out2" SID 262 Position [80, 83, 110, 97] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out3" SID 263 Position [80, 133, 110, 147] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Out4" SID 264 Position [80, 183, 110, 197] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Out5" SID 265 Position [80, 233, 110, 247] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "Out6" SID 266 Position [80, 283, 110, 297] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Out7" SID 267 Position [80, 333, 110, 347] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "Out8" SID 268 Position [80, 383, 110, 397] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "Out9" SID 269 Position [80, 433, 110, 447] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "Out10" SID 270 Position [80, 483, 110, 497] Port "10" IconDisplay "Port number" } Line { SrcBlock "Noise 50" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Noise 55" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "Noise 60" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "Noise 65" SrcPort 1 DstBlock "Out4" DstPort 1 } Line { SrcBlock "Noise 70" SrcPort 1 DstBlock "Out5" DstPort 1 } Line { SrcBlock "Noise 75" SrcPort 1 DstBlock "Out6" DstPort 1 } Line { SrcBlock "Noise 80" SrcPort 1 DstBlock "Out7" DstPort 1 } Line { SrcBlock "Noise 85" SrcPort 1 DstBlock "Out8" DstPort 1 } Line { SrcBlock "Noise 90" SrcPort 1 DstBlock "Out9" DstPort 1 } Line { SrcBlock "Noise 95" SrcPort 1 DstBlock "Out10" DstPort 1 } } } Block { BlockType Outport Name "Out1" SID 183 Position [580, 348, 610, 362] IconDisplay "Port number" } Line { SrcBlock "Multiport\nSwitch" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Subsystem" SrcPort 10 DstBlock "Multiport\nSwitch" DstPort 11 } Line { SrcBlock "Subsystem" SrcPort 9 DstBlock "Multiport\nSwitch" DstPort 10 } Line { SrcBlock "Subsystem" SrcPort 8 DstBlock "Multiport\nSwitch" DstPort 9 } Line { SrcBlock "Subsystem" SrcPort 7 DstBlock "Multiport\nSwitch" DstPort 8 } Line { SrcBlock "Subsystem" SrcPort 6 DstBlock "Multiport\nSwitch" DstPort 7 } Line { SrcBlock "Subsystem" SrcPort 5 DstBlock "Multiport\nSwitch" DstPort 6 } Line { SrcBlock "Subsystem" SrcPort 4 DstBlock "Multiport\nSwitch" DstPort 5 } Line { SrcBlock "Subsystem" SrcPort 3 DstBlock "Multiport\nSwitch" DstPort 4 } Line { SrcBlock "Subsystem" SrcPort 2 DstBlock "Multiport\nSwitch" DstPort 3 } Line { SrcBlock "Subsystem" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Embedded\nMATLAB Function1" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Embedded\nMATLAB Function1" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Embedded\nMATLAB Function1" DstPort 3 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Embedded\nMATLAB Function1" DstPort 4 } Line { SrcBlock "From" SrcPort 1 DstBlock "Embedded\nMATLAB Function1" DstPort 5 } Line { SrcBlock "Embedded\nMATLAB Function1" SrcPort 1 Points [30, 0; 0, -120] DstBlock "Multiport\nSwitch" DstPort 1 } Line { SrcBlock "C5" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 12 } } } Block { BlockType SubSystem Name "OLnoise" SID 217 Ports [0, 1] Position [475, 40, 570, 70] BackgroundColor "green" ShowName off MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskInitialization "load noise.mat " MaskDisplay "disp('Open loop noise')" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "OLnoise" Location [359, 138, 1391, 855] Open off ModelBrowserVisibility on ModelBrowserWidth 212 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Constant Name "Constant1" SID 232 Position [365, 615, 395, 645] Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "Embedded\nMATLAB Function" SID 219 Ports [5, 1] Position [100, 57, 235, 283] PermitHierarchicalResolution "ExplicitOnly" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskDisplay "disp('noise_selection');" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Embedded\nMATLAB Function" Location [257, 457, 812, 717] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark 13 Block { BlockType Inport Name "u" SID 1 Position [20, 101, 40, 119] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Freq" SID 10 Position [20, 136, 40, 154] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Freq1" SID 11 Position [20, 171, 40, 189] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Fbeg" SID 12 Position [20, 206, 40, 224] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "L" SID 13 Position [20, 246, 40, 264] Port "5" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID 7 Ports [1, 1] Position [270, 220, 320, 260] Outputs "1" } Block { BlockType "S-Function" Name " SFunction " SID 6 Tag "Stateflow S-Function Simulator_2 2" Ports [5, 2] Position [180, 100, 230, 220] FunctionName "sf_sfun" PortCounts "[5 2]" EnableBusSupport on Port { PortNumber 2 Name "y" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID 9 Position [460, 231, 480, 249] } Block { BlockType Outport Name "y" SID 5 Position [460, 101, 480, 119] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock "u" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "Freq" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "Freq1" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "Fbeg" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { SrcBlock "L" SrcPort 1 DstBlock " SFunction " DstPort 5 } Line { Name "y" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "y" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } } } Block { BlockType From Name "From" SID 240 Position [40, 246, 80, 274] ShowName off GotoTag "L" TagVisibility "global" } Block { BlockType From Name "From1" SID 272 Position [40, 66, 80, 94] GotoTag "Test" TagVisibility "global" } Block { BlockType From Name "From2" SID 283 Position [40, 111, 80, 139] GotoTag "Freq" TagVisibility "global" } Block { BlockType From Name "From3" SID 284 Position [40, 156, 80, 184] GotoTag "Freq1" TagVisibility "global" } Block { BlockType From Name "From4" SID 285 Position [40, 201, 80, 229] GotoTag "Fbeg" TagVisibility "global" } Block { BlockType MultiPortSwitch Name "Multiport\nSwitch" SID 235 Ports [12, 1] Position [430, 66, 470, 644] Inputs "11" InputSameDT off OutDataType "fixdt(1, 16)" OutScaling "2^0" SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "Subsystem" SID 249 Ports [0, 10] Position [285, 105, 350, 605] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [699, 228, 834, 760] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Noise 50" SID 221 Ports [0, 1] Position [25, 25, 55, 55] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise50p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 55" SID 222 Ports [0, 1] Position [25, 75, 55, 105] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise55p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 60" SID 223 Ports [0, 1] Position [25, 125, 55, 155] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise60p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 65" SID 224 Ports [0, 1] Position [25, 175, 55, 205] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise65p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 70" SID 225 Ports [0, 1] Position [25, 225, 55, 255] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise70p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 75" SID 226 Ports [0, 1] Position [25, 275, 55, 305] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise75p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 80" SID 227 Ports [0, 1] Position [25, 325, 55, 355] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise80p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 85" SID 228 Ports [0, 1] Position [25, 375, 55, 405] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise85p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 90" SID 229 Ports [0, 1] Position [25, 425, 55, 455] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise90p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Reference Name "Noise 95" SID 230 Ports [0, 1] Position [25, 475, 55, 505] LibraryVersion "1.762" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData "off" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" OutValues "noise95p" tsamp "Ts" OutMin "[]" OutMax "[]" OutDataTypeStr "float('double')" OutputDataTypeScalingMode "Specify via dialog" OutDataType "float('double')" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale "off" } Block { BlockType Outport Name "Out1" SID 250 Position [80, 33, 110, 47] IconDisplay "Port number" } Block { BlockType Outport Name "Out2" SID 251 Position [80, 83, 110, 97] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out3" SID 252 Position [80, 133, 110, 147] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Out4" SID 253 Position [80, 183, 110, 197] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Out5" SID 254 Position [80, 233, 110, 247] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "Out6" SID 255 Position [80, 283, 110, 297] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Out7" SID 256 Position [80, 333, 110, 347] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "Out8" SID 257 Position [80, 383, 110, 397] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "Out9" SID 258 Position [80, 433, 110, 447] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "Out10" SID 259 Position [80, 483, 110, 497] Port "10" IconDisplay "Port number" } Line { SrcBlock "Noise 50" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Noise 55" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "Noise 60" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "Noise 65" SrcPort 1 DstBlock "Out4" DstPort 1 } Line { SrcBlock "Noise 70" SrcPort 1 DstBlock "Out5" DstPort 1 } Line { SrcBlock "Noise 75" SrcPort 1 DstBlock "Out6" DstPort 1 } Line { SrcBlock "Noise 80" SrcPort 1 DstBlock "Out7" DstPort 1 } Line { SrcBlock "Noise 85" SrcPort 1 DstBlock "Out8" DstPort 1 } Line { SrcBlock "Noise 90" SrcPort 1 DstBlock "Out9" DstPort 1 } Line { SrcBlock "Noise 95" SrcPort 1 DstBlock "Out10" DstPort 1 } } } Block { BlockType Outport Name "Out1" SID 231 Position [610, 348, 640, 362] IconDisplay "Port number" } Line { SrcBlock "Subsystem" SrcPort 10 DstBlock "Multiport\nSwitch" DstPort 11 } Line { SrcBlock "Subsystem" SrcPort 9 DstBlock "Multiport\nSwitch" DstPort 10 } Line { SrcBlock "Subsystem" SrcPort 8 DstBlock "Multiport\nSwitch" DstPort 9 } Line { SrcBlock "Subsystem" SrcPort 7 DstBlock "Multiport\nSwitch" DstPort 8 } Line { SrcBlock "Subsystem" SrcPort 6 DstBlock "Multiport\nSwitch" DstPort 7 } Line { SrcBlock "Subsystem" SrcPort 5 DstBlock "Multiport\nSwitch" DstPort 6 } Line { SrcBlock "Subsystem" SrcPort 4 DstBlock "Multiport\nSwitch" DstPort 5 } Line { SrcBlock "Subsystem" SrcPort 3 DstBlock "Multiport\nSwitch" DstPort 4 } Line { SrcBlock "Subsystem" SrcPort 2 DstBlock "Multiport\nSwitch" DstPort 3 } Line { SrcBlock "Subsystem" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Embedded\nMATLAB Function" DstPort 1 } Line { SrcBlock "Embedded\nMATLAB Function" SrcPort 1 Points [15, 0; 0, -90] DstBlock "Multiport\nSwitch" DstPort 1 } Line { SrcBlock "Multiport\nSwitch" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Multiport\nSwitch" DstPort 12 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Embedded\nMATLAB Function" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Embedded\nMATLAB Function" DstPort 3 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Embedded\nMATLAB Function" DstPort 4 } Line { SrcBlock "From" SrcPort 1 DstBlock "Embedded\nMATLAB Function" DstPort 5 } } } Block { BlockType DiscreteFilter Name "Primary Path Model" SID 184 Ports [1, 1] Position [320, 67, 380, 103] Numerator "Bp" Denominator "Ap" SampleTime "Ts" } Block { BlockType Saturate Name "Saturation" SID 185 Position [150, 70, 180, 100] UpperLimit "0.7" LowerLimit "-0.7" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Saturate Name "Saturation1" SID 186 Position [145, 155, 175, 185] UpperLimit "0.7" LowerLimit "-0.7" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType DiscreteFilter Name "Secondary Path Model" SID 187 Ports [1, 1] Position [320, 152, 380, 188] Numerator "B" Denominator "A" SampleTime "Ts" } Block { BlockType Sum Name "Sum" SID 188 Ports [2, 1] Position [515, 160, 535, 180] ShowName off IconShape "round" Inputs "++|" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum1" SID 189 Ports [3, 1] Position [610, 155, 640, 185] ShowName off IconShape "round" Inputs "+|+|+" InputSameDT off OutDataTypeMode "Inherit via internal rule" OutDataType "sfix(16)" OutScaling "2^0" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "Out2" SID 190 Position [735, 163, 765, 177] BackgroundColor "cyan" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "U1" SrcPort 1 DstBlock "Saturation1" DstPort 1 } Line { SrcBlock "U" SrcPort 1 DstBlock "Saturation" DstPort 1 } Line { SrcBlock "Primary Path Model" SrcPort 1 Points [140, 0] DstBlock "Sum" DstPort 1 } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "Saturation" SrcPort 1 DstBlock "Primary Path Model" DstPort 1 } Line { SrcBlock "Saturation1" SrcPort 1 DstBlock "Secondary Path Model" DstPort 1 } Line { SrcBlock "Secondary Path Model" SrcPort 1 DstBlock "Sum" DstPort 2 } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "CLnoise" SrcPort 1 Points [50, 0] DstBlock "Sum1" DstPort 3 } Line { SrcBlock "OLnoise" SrcPort 1 Points [50, 0] DstBlock "Sum1" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID 216 Ports [1] Position [650, 184, 680, 216] Floating off Location [753, 403, 1275, 672] Open off NumInputPorts "1" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" } YMin "-0.1" YMax "0.1" SaveToWorkspace on SaveName "yyy" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { Name "u(t)" Labels [0, 0] SrcBlock "Controller" SrcPort 1 Points [110, 0] Branch { DstBlock "Plant" DstPort 2 } Branch { Points [0, -50] DstBlock "Mux1" DstPort 2 } } Line { Name "y(t)" Labels [0, 0] SrcBlock "Plant" SrcPort 1 Points [45, 0] Branch { DstBlock "Mux1" DstPort 3 } Branch { Points [0, 80; -500, 0; 0, -65] DstBlock "Controller" DstPort 1 } } Line { SrcBlock "0 : OL\n1 : CL" SrcPort 1 Points [0, 5] Branch { DstBlock "Controller" DstPort enable } Branch { DstBlock "Goto" DstPort 1 } } Line { SrcBlock "Disturbances" SrcPort 1 Points [170, 0; 0, 50] Branch { Points [0, 60] DstBlock "Plant" DstPort 1 } Branch { Points [230, 0] DstBlock "Mux1" DstPort 1 } } } } # Finite State Machines # # Stateflow Version 7.1 (R2009a) dated Jul 17 2009, 10:24:20 # # Stateflow { machine { id 1 name "Simulator_2" created "02-Oct-2009 16:36:44" isLibrary 0 firstTarget 24 sfVersion 71014000.00001 } chart { id 2 name "Plant/CLnoise/Embedded\nMATLAB Function1" windowPosition [420.75 158.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.333333333333333] treeNode [0 3 0 0] firstTransition 5 firstJunction 4 viewObj 2 machine 1 ssIdHighWaterMark 9 decomposition CLUSTER_CHART type EML_CHART firstData 6 chartFileNumber 1 disableImplicitCasting 1 eml { name "noise_selection" } supportVariableSizing 0 } state { id 3 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 2 treeNode [2 0 0 0] superState SUBCHART subviewer 2 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function y = noise_selection(u,Freq,Freq1,Fbeg,L)\n% This block supports the Embedded MATLAB subs" "et.\n% See the help menu for details. \nif L==1\n if u==1\n f=Freq;\n elseif u==2\n f=Freq1;" "\n else\n f=Fbeg;\n end\n if f(1)>=50 && f(1)<55\n y=1;\n elseif f(1)>=55 && f(1)<60\n" " y=2;\n elseif f(1)>=60 && f(1)<65\n y=3;\n elseif f(1)>=65 && f(1)<70\n y=4;\n el" "seif f(1)>=70 && f(1)<75\n y=5;\n elseif f(1)>=75 && f(1)<80\n y=6;\n elseif f(1)>=80 && f(1" ")<85\n y=7;\n elseif f(1)>=85 && f(1)<90\n y=8;\n elseif f(1)>=90 && f(1)<95\n y=9;\n" " else\n y=10;\n end\nelse\n y=11;\nend\n \n " editorLayout "100 M4x1[264 374 671 364]" fimathString "fimath(...\n'RoundMode', 'floor',...\n'OverflowMode', 'wrap',...\n'ProductMode', 'KeepLSB', " "'ProductWordLength', 32,...\n'SumMode', 'KeepLSB', 'SumWordLength', 32,...\n'CastBeforeSum', true)" fimathForFiConstructors FimathMatlabFactoryDefault emlDefaultFimath FimathUserSpecified } } junction { id 4 position [23.5747 49.5747 7] chart 2 linkNode [2 0 0] subviewer 2 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 5 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 4 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 2 linkNode [2 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 2 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 6 ssIdNumber 4 name "u" linkNode [2 0 7] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE } complexity SF_COMPLEX_INHERITED } dataType "Inherit: Same as Simulink" } data { id 7 ssIdNumber 5 name "y" linkNode [2 6 8] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 8 ssIdNumber 6 name "Freq" linkNode [2 7 9] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 9 ssIdNumber 7 name "Freq1" linkNode [2 8 10] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 10 ssIdNumber 8 name "Fbeg" linkNode [2 9 11] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 11 ssIdNumber 9 name "L" linkNode [2 10 0] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 12 name "Plant/CLnoise/Embedded\nMATLAB Function1" machine 1 chart 2 } chart { id 13 name "Plant/OLnoise/Embedded\nMATLAB Function" windowPosition [405.75 173.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.333333333333333] treeNode [0 14 0 0] firstTransition 16 firstJunction 15 viewObj 13 machine 1 ssIdHighWaterMark 9 decomposition CLUSTER_CHART type EML_CHART firstData 17 chartFileNumber 2 disableImplicitCasting 1 eml { name "noise_selection" } supportVariableSizing 0 } state { id 14 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 13 treeNode [13 0 0 0] superState SUBCHART subviewer 13 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function y = noise_selection(u,Freq,Freq1,Fbeg,L)\n% This block supports the Embedded MATLAB subs" "et.\n% See the help menu for details. \nif L==0\n if u==1\n f=Freq;\n elseif u==2\n f=Freq1;" "\n else\n f=Fbeg;\n end\n if f(1)>=50 && f(1)<55\n y=1;\n elseif f(1)>=55 && f(1)<60\n" " y=2;\n elseif f(1)>=60 && f(1)<65\n y=3;\n elseif f(1)>=65 && f(1)<70\n y=4;\n el" "seif f(1)>=70 && f(1)<75\n y=5;\n elseif f(1)>=75 && f(1)<80\n y=6;\n elseif f(1)>=80 && f(1" ")<85\n y=7;\n elseif f(1)>=85 && f(1)<90\n y=8;\n elseif f(1)>=90 && f(1)<95\n y=9;\n" " else\n y=10;\n end\nelse\n y=11;\nend\n \n " editorLayout "100 M4x1[264 374 671 364]" fimathString "fimath(...\n'RoundMode', 'floor',...\n'OverflowMode', 'wrap',...\n'ProductMode', 'KeepLSB', " "'ProductWordLength', 32,...\n'SumMode', 'KeepLSB', 'SumWordLength', 32,...\n'CastBeforeSum', true)" fimathForFiConstructors FimathMatlabFactoryDefault emlDefaultFimath FimathUserSpecified } } junction { id 15 position [23.5747 49.5747 7] chart 13 linkNode [13 0 0] subviewer 13 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 16 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 15 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 13 linkNode [13 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 13 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 17 ssIdNumber 4 name "u" linkNode [13 0 18] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE } complexity SF_COMPLEX_INHERITED } dataType "Inherit: Same as Simulink" } data { id 18 ssIdNumber 5 name "y" linkNode [13 17 19] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 19 ssIdNumber 6 name "Freq" linkNode [13 18 20] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 20 ssIdNumber 7 name "Freq1" linkNode [13 19 21] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 21 ssIdNumber 8 name "Fbeg" linkNode [13 20 22] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 22 ssIdNumber 9 name "L" linkNode [13 21 0] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 23 name "Plant/OLnoise/Embedded\nMATLAB Function" machine 1 chart 13 } target { id 24 name "sfun" codeFlags "" machine 1 linkNode [1 0 25] } target { id 25 name "rtw" codeFlags " comments=1 statebitsets=1 databitsets=1 emitlogicalops=1 elseifdetection=1 constantfolding=1 redu" "ndantloadelimination=0 preservenames=0 preservenameswithparent=0 exportcharts=0" machine 1 linkNode [1 24 0] } }